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Source Coding Scheme DM/ADM Encoder and Decoder
Experiments:
- To monitor and measure the various control signals.
- Data rate / Selected clock
- Analog signals - Sine/Square/Triangle
- To monitor the characteristics of DM/ADM encoder block
- Selected clock
- Sampled input signal
- Up / Down counter
- DAC output
- DM/ADM output
- To measure the characteristics of DAC output with different step sizes
- Selected clock
- DAC output
- To study the slope overload and Quantization error
- Clock signal
- Frame pulse signals
- DAC output
- Final output
- Observation of automatic step size variation in ADM.
- To measure the characteristics of DM/ADM decoder and sampling theorem verification by varying the frequency of input and clock frequency.
Technical Specification:
| ENCODER |
| SINE / TRIANGULAR / SQUARE INPUT SIGNAL |
| AMPLITUDE | 2 VPP |
| FREQUENCY | 0.5 - 4KHz |
| DC SIGNAL | (+/-)5v |
| DATA RATE | 8/16/32/64 KHz and Ext Clock |
| WORD LENGTH | 8 bits |
| STEP | Variable by changing DIP switch settings |
| UP/DOWN COUNTER | 4029 |
| DAC |
| WORD LENGTH | 8 bits |
| RESOLUTION | 40 mV |
| CONVERSION TIME | 100 - 116ms |
| OPERATING VOLTAGE | 5VDC |
| OPERATING CURRENT | < 10 mamps |
Features:
- All IC's are mounted on machined IC base
- PCB's are SMOBC finished with glass epoxy coating
- Multi color printed block diagram is given on the top of the kit
- Testing point at the end of each functional block
- 28 or 256 data pattern combinations available through dip switches
- The trainer kit is enclosed in fiber glass box for safe keep.
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